// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    : pingpang_ctrl.v
// Module name  : pingpang_ctrl
// Full name    :  
//
// Author       : Hbing
// Email        : 2629029232@qq.com
// Data         : 2020/9/12
// Version      : V 1.0 
// 
// Abstract     : 
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 待完成 -- 修改为两路汇聚的crossbar_ctl--已完成
// 
// 
// *****************************************************************
// `include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 3*3交叉节点，但是为了防止阻塞，第三列交叉节点中的乒乓RAM翻倍，分别存port2,port3目的端口的数据帧
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
module crossbar_ctl_2(
    //sysrem input/output
    input  wire         clk                 ,
    input  wire         rst_n               ,
    input wire   [9:0]  ram_2p_cfg_register,
    //10G--01
    //with bus_master_tx
    input  wire [255:0] emac_data_in0       ,
    input  wire         emac_data_wren0     ,
    input  wire [  5:0] rx_address_dpram0   ,
    input  wire         mul_indicate0       ,
    output wire         uni_buffer_val0     ,
    output wire         mul_buffer_val0     ,
    //with MAC_IP
    input  wire         emac_rx_ready0      ,
    output wire [255:0] emac_data_final0    ,
    output wire         emac_dval_final0    ,
    output wire         emac_dsav_final0    ,
    output wire         emac_sop_final0     ,
    output wire         emac_eop_final0     ,
    output wire [  4:0] emac_mod_final0     ,
    output wire [  3:0] mac_dest_port_out0  ,
    output wire         uni_out_busy0       ,
    output wire         mul_out_busy0       ,
    input  wire         out_enable0         ,
    output wire [ 10:0] emac_len_final0     ,
    //output wire [  2:0] emac_pri_final0     ,
    output wire         read_finish0        ,
    //10G--02
    //with bus_master_tx
    input  wire [255:0] emac_data_in1       ,
    input  wire         emac_data_wren1     ,
    input  wire [  5:0] rx_address_dpram1   ,
    input  wire         mul_indicate1       ,
    output wire         uni_buffer_val1     ,
    output wire         mul_buffer_val1     ,
    //with MAC_IP
    input  wire         emac_rx_ready1      ,
    output wire [255:0] emac_data_final1    ,
    output wire         emac_dval_final1    ,
    output wire         emac_dsav_final1    ,
    output wire         emac_sop_final1     ,
    output wire         emac_eop_final1     ,
    output wire [  4:0] emac_mod_final1     ,
    output wire [  3:0] mac_dest_port_out1  ,
    output wire         uni_out_busy1       ,
    output wire         mul_out_busy1       ,
    input  wire         out_enable1         ,
    output wire [ 10:0] emac_len_final1     ,
    //output wire [  2:0] emac_pri_final1     ,
    output wire         read_finish1        

);
//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

//交叉节点乒乓RAM写入w256-d64
//6'b000000--队列号-帧长-目的端口列表
//6'b000001--SRAM_memory读出的数据
//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
//状态机

//WIRES


//*********************
//INSTANTCE MODULE
//*********************
    crossbar_ctl inst_crossbar_ctl0(
            .clk               (clk),
            .rst_n             (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            .emac_data_in      (emac_data_in0),
            .emac_data_wren    (emac_data_wren0),
            .rx_address_dpram  (rx_address_dpram0),
            .mul_indicate      (mul_indicate0),
            .uni_buffer_val    (uni_buffer_val0),
            .mul_buffer_val    (mul_buffer_val0),
            .emac_rx_ready     (emac_rx_ready0),
            .emac_data_final   (emac_data_final0),
            .emac_dval_final   (emac_dval_final0),
            .emac_dsav_final   (emac_dsav_final0),
            .emac_sop_final    (emac_sop_final0),
            .emac_eop_final    (emac_eop_final0),
            .emac_mod_final    (emac_mod_final0),
            .mac_dest_port_out (mac_dest_port_out0),
            .uni_out_busy      (uni_out_busy0),
            .mul_out_busy      (mul_out_busy0),
            .out_enable        (out_enable0),
            .emac_len_final    (emac_len_final0),
            //.emac_pri_final    (emac_pri_final0),
            .read_finish       (read_finish0)
        );

    crossbar_ctl inst_crossbar_ctl1(
            .clk               (clk),
            .rst_n             (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            .emac_data_in      (emac_data_in1),
            .emac_data_wren    (emac_data_wren1),
            .rx_address_dpram  (rx_address_dpram1),
            .mul_indicate      (mul_indicate1),
            .uni_buffer_val    (uni_buffer_val1),
            .mul_buffer_val    (mul_buffer_val1),
            .emac_rx_ready     (emac_rx_ready1),
            .emac_data_final   (emac_data_final1),
            .emac_dval_final   (emac_dval_final1),
            .emac_dsav_final   (emac_dsav_final1),
            .emac_sop_final    (emac_sop_final1),
            .emac_eop_final    (emac_eop_final1),
            .emac_mod_final    (emac_mod_final1),
            .mac_dest_port_out (mac_dest_port_out1),
            .uni_out_busy      (uni_out_busy1),
            .mul_out_busy      (mul_out_busy1),
            .out_enable        (out_enable1),
            .emac_len_final    (emac_len_final1),
            //.emac_pri_final    (emac_pri_final1),
            .read_finish       (read_finish1)
        );


//*********************
//MAIN CORE
//********************* 


endmodule
